Protocol++® v5.7.0 (Protocolpp®)
Connecting the World One Device at a Time 

Encryption Algorithms

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Protocol++® includes support for most encryption algorithms found in the various IEEE, NIST, and IETF standards and the modes of operation necessary to support the protocols found at www.protocolpp.com.  If detected at run time, several algorithms will use hardware acceleration for processing.

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• x86, x64 (x86-64) hardware acceleration used when detected (feature has been enabled for several years)

  • run-time CPU feature detection and code selection

  • supports GCC-style and MSVC-style inline assembly, and MASM for x64

  • x86, x64 (x86-64), x32 provides SSE2, SSE4 and AVX implementations

  • AES, CRC, GCM and SHA use ARM, Intel and PowerPC hardware acceleration when available

  • Random data generation uses SIMD instructions

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Included algorithms are:

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• Advanced Encryption Standard (AES - hardware accelerated)

  • AES-ECB

  • AES-CBC

  • AES-CTR

  • AES-GCM

  • AES-CCM

  • AES-XTS

• CHACHA20 (hardware accelerated) Stream cipher

• SM4 (hardware accelerated)- Chinese block cipher

  • SM4-CBC

  • SM4-CTR

  • SM4-GCM

  • SM4-CCM

• SNOW3G

  • F8 cipher

• SnowV

  • GCM

  • GHASH

• ZUC

  • F8 cipher

  • 128-bit key​

• ZUC-256

  • 16- and 25-byte IVs

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Conformance

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Validated against all conformance vectors available using CPPUNIT tests (screen capture of cppunit test below)

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